Raspberry Pi /RP2350 /I2C0 /IC_DATA_CMD

This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.

Reset value: 0x0

This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.

When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a ‘don’t care’ because writes to this register are not required. In slave-transmitter mode, a ‘0’ indicates that the data in IC_DATA_CMD is to be transmitted.

When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a ‘1’ is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.

Reset value: 0x0

0 (WRITE): Master Write Command

1 (READ): Master Read Command

This bit controls whether a STOP is issued after the byte is sent or received.

• 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0

0 (DISABLE): Don’t Issue STOP after this command

1 (ENABLE): Issue STOP after this command

This bit controls whether a RESTART is issued before the byte is sent or received.

1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.

0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.

Reset value: 0x0

0 (DISABLE): Don’t Issue RESTART before this command

1 (ENABLE): Issue RESTART before this command

Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.

Reset value : 0x0

NOTE: In case of APB_DATA_WIDTH=8,

1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.

2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).

3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status.

0 (INACTIVE): Sequential data byte received

1 (ACTIVE): Non sequential data byte received